Hitachi Develops Wiring Reduction Technology for Scalable Silicon Quantum Computers

Hitachi has announced a new 'shared-gate architecture' technology designed to significantly reduce the wiring complexity in silicon-based quantum computers. In collaboration with imec, the company successfully prototyped a 16-qubit array structure on a 300-millimeter wafer, confirming partial qubit operation. This breakthrough addresses a major scaling barrier for quantum computing, with a goal of achieving 100-qubit systems by fiscal 2028 and 1,000-qubit systems by fiscal 2030.